The basic idea behind fractional calculus is that it considers derivatives and integrals of non-integer orders giving extra degrees of freedom and tuning knobs for modeling complex and memory dependent systems with compact descriptions. This paper reviews fractional calculus history, theory, and its applications in electrical engineering. The basic definitions of fractional calculus are presented together with some examples. Integer order transfer function approximations and constant phase elements (CPEs) emulators are overviewed due to their importance in implementing fractional-order

This work introduces a new successive approximation register circuit (SAR) for SAR analog to digital converter (ADC) based on Dynamic Random Access Memory (DRAM) cells. Based on the proposed DRAM based SAR ADC and a differential capacitive DAC, a 10-bit 2V ADC is designed in 0.18um CMOS technology. The proposed SAR is compared to traditional SAR to verify that the proposed SAR decreases the power of SAR ADC for biomedical applications. The power consumption for the proposed SAR ADC is found to be 26.24uW with ENOB equal to 9.26, and the maximum sampling frequency is 1MHz. For the traditional

The paper proposes voltage-controlled first-and second-order memristor emulators. The emulators are designed using an operational-transconductance amplifier (OTA) and voltage multiplier blocks plus a fractional-order capacitor. The presented second-order emulator provides two pinched points controlled by order of the employed fractional-order capacitor. Numerical and PSPICE simulation results using AD844 and AD633 are introduced for different cases to validate the theoretical findings. The experimental verification is presented, showing the design flexibility and controllability based on the

Different generalized filters topologies are proposed in the fractional-order domain. Three voltage-mode topologies and one current-mode topology are used to realize several types of fractional-order filters by applying different admittances combinations. The proposed topologies are designed using a single second-generation current conveyor (CCII-) and two fractional-order capacitors, which add more degrees of freedom for the design. The generalized Fractional Transfer Function (FTF) for each proposed topology is investigated where the fractional-order low-pass, band-pass, high-pass, and notch

This paper proposes a safe and effective method to generate the subkeys that are used in the Advanced Encryption Standard (AES) algorithm for data encryption applications. The suggested method relies upon the Pseudo-Random Number Generator (PRNG) that is created from the improved Lorenz chaotic system. The output of PRNG is exploited as a key schedule for generating AES subkeys where the output is characterized by having an infinite periodic length. This method can be used in high-speed applications since no hardware multipliers are utilized so it gives the best hardware performance

This brief proposes a method of generating custom-shaped attractors, which depends on a planarly rotating V-shape multi-scroll chaotic system with offset boosting and amplitude control, and its FPGA verification. The proposed planarly rotating, translational (offset boostable), and scalable (amplitude controllable) system exhibits a wide basin of attraction and can cover the whole space. Consequently, non-autonomous parameters enable generating attractors of custom-shapes, e.g., letters of the English alphabet as a demonstrating example. Furthermore, non-autonomous parameters are employed to

Recently, pinched hysteresis has been found in the electrical modelling of regular plant tissues. Usually, the biological tissues are characterized in the frequency domain using bio-impedance analyzers without investigating the time domain, which would show the pinched hysteresis. In this paper, the current-voltage analysis of some of the widely known electrical bio-impedance models is studied. The investigated models are the single dispersion Cole-impedance model, the double dispersion Cole-impedance model and the fractional-order simplified Hayden model to prove that these models can not

Ternary logic has become a promising alternative to traditional binary logic due to low power consumption and reduced circuits such as interconnects and chip areas. The efficiency of the multiplier circuit can be much better using a ternary logic system. Carbon nanotube field-effect transistor (CNTFET) is a promising technology as it achieves more advantages than MOSFET due to its low off-current features such as low power and high performance. This paper presents a comparative study of four implementations of a 1-trit multiplier based on CNTFET technology. The comparison is performed in terms

Image enhancement is better achieved when fractional-order masks are used rather than integer-order ones, this is due to the flexibility of fractional-order parameters control. This paper proposes a combination of fractional-order masks to be used in parallel as double filters system structure to improve image enhancement rather than using a single-stage filter. Various performance metrics are used in this work to evaluate the proposed system, such as Information Entropy (IE), Average Gradient (AG), Structural Similarity Index Metric (SSIM) and Peak Signal to Noise Ratio (PSNR). Based on

Analysis and optimization of switched-capacitor (SC) dc-dc converters with a series inductive filter are developed. The steady-state output impedance of such SC resonant converters is calculated for a 21 conversion ratio. In addition, the necessary conditions for proper application of the output inductive filter are derived. The proposed optimization methodology applies numerical optimization to evaluate different loss components in order to find the optimal design point of highest conversion efficiency. This optimization method is verified through SPICE simulations on a 21 SC power stage in