Multilevel electronic systems offer the reduction of implementation’ complexity, power consumption, and area. Ternary system is a very promising system where more information is represented in the same number of digits compared to the binary systems. In this paper, ternary logic gates and some of their ternary circuit applications are presented using memristors and CNTFET inverter. This integration between memristors and CNTFET offers low static power, small area and high performance. The proposed circuits do not require refreshment like the previously published circuits and are not initial

The approximations of fractional-order differentiator/integrator transfer functions are currently performed using integer-order rational functions, which are in general implemented through appropriate multi-feedback topologies. The spreading in the values of time-constants and scaling factors, needed to implement these topologies, increases as the order of the differentiator/integrator and/or the order of the approximation increases. This leads to non-practical values of capacitances and resistances/transconductances in the implementation. A solution to overcome this obstacle is introduced in

Fractional-order lead/lag compensator realizations, using Operational Transconductance Amplifiers as active blocks, are presented in this paper. Two different types of fractional-order transfer functions, derived from the integer-order lead/lag compensator transfer function, are used to describe the behavior of the fractional-order compensator. Both types are approximated using the Padé approximation tool, and are expressed by the same form of rational integer-order transfer function. This means that both types can be implemented using the same active core, which is an important advantage from

In this paper, the application of the theory of Lissajous figures to the creation of pinched hysteresis loops, considered to be a characteristic of memristive systems, is demonstrated and experimentally verified using designed electronic circuits in the form of an input impedance. The relationship between the Lissajous-based model of the pinched hysteresis loop and a previously reported integrator-multiplier model is clarified. Important special cases are highlighted and necessary conditions to obtain a pinch point, loops with positive or negative inclination, as well as no pinch point are

A low frequency relaxation oscillator is designed using a super-capacitor. An accurate analytical expression for the oscillation frequency is derived based on a fractional-order super-capacitor model composed of a resistance in series with a Constant Phase Element (CPE) whose pseudo-capacitance and dispersion coefficient are determined using impedance spectroscopy measurements. Experimental results confirm our theoretical analysis. © 2016 Elsevier GmbH. All rights reserved.

This paper presents a comprehensive method and analysis on the design of two-transistor multi-output filters where three possible functions are simultaneously available. Although two transistors are employed at its core, proper biasing does not require additional passive components. A total of thirteen valid second-order filters are reported, and several of them are experimentally tested using discrete transistors as well as simulated using Spectre in a BiCMOS process. A fully differential realization of a MOS-C band-pass filter, based on one of the structures found, is designed and then used

This paper introduces the concept of fractional-order complex Chebyshev filter. A fractional variation of Chebyshev differential equations is introduced based on Caputo fractional operator. The proposed equation is solved using fractional Taylor power series method. The condition for fractional polynomial solutions is obtained and the first four polynomials scaled using an appropriate scaling factor. The fractional-order complex Chebyshev low-pass filter based on the obtained fractional polynomials is developed. Two methods for obtaining the transfer functions of the complex filter are

This paper discusses the implementation sensitivity of chaotic systems added to their widely discussed sensitivities to initial conditions and parameter variation. This sensitivity can cause mismatches in some applications, which require an exact duplication of the system, e.g., chaos-based cryptography, synchronization and communication. Specifically, different implementation cases of three discretized jerk-based chaotic systems and a discrete-time logistic map are presented corresponding to different orders of additions and multiplications. The cases exhibit roughly similar attractor shapes

The efficiency of the hardware implementations of fractional-order systems heavily relies on the efficiency of realizing the fractional-order derivative operator. In this work, a generic hardware implementation of the fractional-order derivative based on the Grünwald–Letnikov’s approximation is proposed and verified on a field-programmable gate array. The main advantage of this particular realization is its flexibility in applications which enable easy real-time configuration of the values of the fractional orders, step sizes, and/or other system parameters without changing the hardware

In this work, we demonstrate the possibility of performing two-dimensional rotation on a chaotic system. This enables the rotation of its attractor in space without changing its chaotic dynamics. In particular, the rotated system preserves the same eigenvalues at all equilibrium points and its largest Lyapunov exponent remains unchanged. Two chaotic systems, one of which is the classical Lorenz system, are used to illustrate and validate the rotation operation using numerical simulations and further experimentally using a digital FPGA platform. © 2019, Springer Science+Business Media, LLC