about.jpg

A new method to synchronize fractional chaotic systems with different dimensions

By using two scaling function matrices, the synchronization problem of different dimensional fractional order chaotic systems in different dimensions is developed in this chapter. The controller is designed to assure that the synchronization of two different dimensional fractional order chaotic systems is achieved using the Lyapunov direct method.Numerical examples and computer simulations are used to validate numerically the proposed synchronization schemes. © Springer International Publishing AG 2017.

Circuit Theory and Applications

Stochastic analysis for one dimensional photonic crystals

Tolerance variations of the design parameters of the photonic crystals due to fabrication processes have a strong effect on the performance of the photonic crystals and their operating wavelengths. In this work, the uncertainties of the design parameters of one-dimensional photonic crystals (1D-PCs) and their impacts on the PCs optical properties and the operating performance are investigated. The effects of these uncertainties for different tolerances are studied for both defect-free PCs and PCs with a defect air layer. The probability distribution function and the standard deviations of the

Circuit Theory and Applications

Realizations of fractional-order PID loop-shaping controller for mechatronic applications

A novel procedure for the realization of a fractional-order PID loop-shaping controller, suitable for precision control of mechatronic systems, is introduced in this work. Exploiting appropriate tools, the controller function is approximated as a whole, leading to a simple form of integer-order approximation, when compared to the case where each intermediate part of the PID transfer function is approximated. This leads to a direct implementation, composed of conventional active and passive elements. Simulation and experimental results, derived from the OrCAD PSpice simulator and a Field

Circuit Theory and Applications

Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture

Multipliers are a major energy and delay contributor in modern compute-intensive applications due to their complex logic architecture. As such, designing multipliers with reduced energy and faster speed has remained a thoroughgoing challenge. This paper presents a novel, carry-free multiplier, which is suitable for a new-generation of energy-constrained applications. The multiplier circuit consists of an array of memristor-transistor cells that can be selected (i.e., turned ON or OFF) using a combination of DC bias voltages based on the operand values. When a cell is selected it contributes to

Circuit Theory and Applications

Enhancing the improved Howland circuit

In this paper, an enhanced version of the improved Howland circuit is proposed. An improvement in output impedance to a maximum factor of two is obtained. The theoretical derivation is presented, including analysis from a two-port network perspective, and both simulation and experimental results using a general purpose opamp confirm the expected result. © 2019 John Wiley & Sons, Ltd.

Circuit Theory and Applications

Power-law compensator design for plants with uncertainties: Experimental verification

A power-law compensator scheme for achieving robust frequency compensation in control systems including plants with an uncertain pole, is introduced in this work. This is achieved through an appropriate selection of the compensator parameters, which guarantee that the Nyquist diagram of the open-loop system compensator-plant crosses a fixed point independent of the plant pole variations. The implementation of the fractional-order compensator is performed through the utilization of a curve-fitting-based technique and the derived rational integer-order transfer function is realized on a Field

Circuit Theory and Applications

On chip 0.5 V 2 GHz four-output quadrature-phase oscillator

In this paper, we present a quadrature-phase oscillator that can provide four output voltages while operating from a single 0.5 V supply. The oscillator is based on two cross-coupled modified differential pair cells and provides signals with a phase difference of ±180° or ±90° depending on the chosen output nodes. A test chip with an active area of 0.175 mm2 was designed and fabricated in a 65-nm CMOS process and its measurement results show a phase noise of −119.5 dBc/Hz at 1 MHz offset from a carrier frequency of 1.967 GHz while consuming 6.15mW. Finally, experimental results show a FoM of

Circuit Theory and Applications

Spectral Capacitance of Series and Parallel Combinations of Supercapacitors

The porous nature of the electrode material in supercapacitors and the apparent conductivity of the electrolyte cause their impedance to show a complex frequency-dependent behavior, which in turn makes it incorrect to treat them as ideal capacitors, even at a frequency of a few millihertz. This is particularly crucial if the intended application requires a configuration that uses stacked supercapacitor banks, in which errors in defining the metrics of the individual components accumulate. Although manufacturers provide supercapacitor ratings under DC only, by using a detailed impedance

Circuit Theory and Applications

Enhancing CSP using Spot Fresnel Lens and SiC Coating

Concentrated Solar Power (CSP) systems have a good potential as a renewable energy candidate that are based on converting the incident solar thermal energy to an electrical energy. In this paper, CSP using spot Fresnel lens instead of traditional lenses is presented to enhance the efficiency of the system, where Silicon Carbide (SiC) is used as a coating material for the receiver of the system due to its high thermal conductivity. The presented prototype has been investigated for uncoated spot Fresnel lens CSP, and for spot Fresnel lens CSP with the SiC as a coating material showing the

Circuit Theory and Applications

Realization of fractional-order capacitor based on passive symmetric network

In this paper, a new realization of the fractional capacitor (FC) using passive symmetric networks is proposed. A general analysis of the symmetric network that is independent of the internal impedance composition is introduced. Three different internal impedances are utilized in the network to realize the required response of the FC. These three cases are based on either a series RC circuit, integer Cole-impedance circuit, or both. The network size and the values of the passive elements are optimized using the minimax and least m th optimization techniques. The proposed realizations are

Circuit Theory and Applications