As the usage of very large scale integration (VLSI) in computers continues to increase, debugging of timing problems on actual hardware becomes more and more difficult. The post-layout gate-level simulation constitutes a critical design step for timing closure. The major drawback of traditional post-layout gate-level simulation is its long analysis time, which increases as design complexity increases. An alternative method is static timing analysis (STA), which can reduce analysis time. Going deeper through the nanometer technology, new STA techniques have to be present to provide more

This paper represents a new self timed signaling technique for low power SerDes transceiver. A three level coding technique enables extracting the clock from the data using simple phase detector rather than using complex power hungry blocks such as Clock Data Recovery (CDR) or a Phase Locked Loop (PLL). This SerDes transceiver was implemented using 90nm TSMC technology. The transmitter serializes 8 parallel bits at 1.125GHz, and multiplexes the 10Gbps serial data stream with a 20GHz clock on a single line using three level signaling. The total power consumed in the Tx/Rx pair with the

A novel ripple mitigation technique is proposed for switched-capacitor voltage regulators (SCVR), which eliminates the output voltage ripple without using multi-phase interleaving. An inner control loop matches the SCVR's switch current to the load current on a cycle by cycle basis. A 2-phase 32 SCVR is designed in 45-nm CMOS process with the proposed control. For a 1.8 V to 1.05 V /40 mA converter, the proposed mitigation loop reduces the peak-to-peak output ripple from 330 mVp-p to 17 mVp-p, using total output capacitance of 4 nF/A. In addition, the proposed technique yields excellent

This paper discusses the influence of the fractional order parameter on conventional chaotic systems. These fractional-order parameters increase the system degree of freedom allowing it to enter new domains and thus it can be used as a control for such dynamical systems. This paper investigates the behaviour of the equally-fractional-order Lü chaotic system when changing the fractional-order parameter and determines the fractional-order ranges for chaotic behaviour. Five different parameter values and six fractional-order cases are discussed through this paper. Unlike the conventional

A few special chaotic systems without unstable equilibrium points have been investigated recently. It is worth noting that these special systems are different from normal chaotic ones because the classical Shilnikov criterion cannot be used to prove chaos of such systems. A novel unusual chaotic system without equilibrium is proposed in this work. We discover dynamical properties as well as the synchronization of the new system. Furthermore, a physical realization of the system without equilibrium is also implemented to illustrate its feasibility. © 2017 Ahmad Taher Azar et al.

In this paper the variability of supercapacitor fractional-order model parameters are explored when extracted using a non-linear least squares optimization applied to their constant current discharging behaviour. The variability of parameters extracted 1000 different times applying the optimization process to multiple sets of simulated and experimental data are presented to validate this approach. The experimental results were collected from 4 samples of Panasonic EEC-SSR5H105 supercapacitors (1 F rating) acting as a secondary power source for an Arduino Uno system. Simulations using the

A simple realization of the fractional-order Mihalas-Niebur neuron model is presented in this work. The required low-pass filter is implemented using current-mirrors offering simple circuitry and, also, electronic tunability of the realized time-constant. Due to the limited bandwidth required for this application, the necessary fractional-order capacitor is realized using an appropriately configured second-order RC network. The proposed realization highlights the connection between the fractional-order and the frequency spiking of the model through appropriate simulation results, which are

In this study, we show that the discharge voltage pattern of a supercapacitor exhibiting fractional-order behavior from the same initial steady-state voltage into a constant resistor is dependent on the past charging voltage profile. The charging voltage was designed to follow a power-law function, i.e. [Formula: see text], in which [Formula: see text] (charging time duration between zero voltage to the terminal voltage [Formula: see text]) and p ([Formula: see text]) act as two variable parameters. We used this history-dependence of the dynamic behavior of the device to uniquely retrieve

Functional dye molecules, such as porphyrins, attached to CdSe quantum dots (QDs) through anchoring meso-pyridyl substituents, form quasi-stable nanoassemblies. This fact results in photoluminescence (PL) quenching of the QDs both due to Förster resonance energy transfer (FRET) and the formation of non-radiative surface states under conditions of quantum confinement (non-FRET). The formation process is in competition with the ligand dynamics. At least two timescales are found for the formation of the assemblies: 1) one faster than 60 s attributed to saturation of empty attachment sites and 2)

Well-defined ultra-thin ‘wire’ like cadmium sulfide (CdS) nanostructures have been synthesized by applying simple cost-effective hydrothermal route. The content of nanostructures modifies the nature of surface interaction between two liquid crystal (LC) components as revealed by optical and electrical investigation. Those synthesized nanowires have an average diameter of about 7–10 nm and length up to several micrometers region. A possible mechanism has been proposed and the addition of cataionic surfactant cetyltrimethylammonium bromide (CTAB) into the two mixed-solvents would play an