This paper posits an automatic handling to some of the most common RTL critical issues in the verification process. In this paper, we propose an automatic linting tool to handle some causes of intentional latches generated in the synthesis process and clock gating timing violation. Therefore, no need to waste verification time to dive through long codes to handle them manually. The proposed tool has been implemented using python to speed up the linting process with easy GUI. Finally, it has been tested on OpenCore certificated projects source codes. © 2018 IEEE.

This paper proposes new multi-scrolls chaotic systems which is called the X-shape. The purpose is to have more complex systems and flexible ranges of the chaotic behavior. The proposed X-shape is a combination between V-shape and Λ-shape. This paper also represents the Heart-shape which considered a special case of the X-shape. The system complexity has been measured by MLE and compared with V-shape system. It shows lager MLE on the side of X-shape. In addition, the effect of changing system parameters has been discussed and compared with V-shape. Finally, a fully hardware implantation on FPGA

The promising capabilities of fractional-order devices challenge researchers to find a way to build it physically. Approximating the Laplacian operator sα can pave the way to emulate the fractional-order devices till its off-the-shelf appearance. This paper introduces three approximations of the Laplacian operator sα: Oustaloup, Matsuda, and Valsa by comparing their behaviors through two types of oscillator circuits. The first two are well-established approximations and the latter is proposed for the first time by converting its model network to an integer polynomial approximation of the

This paper introduces closed formulas of two topologies of fractional-order relaxation oscillators. One of these topologies is based on Operational Amplifier (Op-Amp) and the other one depends on Operational Operational Trans-Resistance Amplifier (OTRA). Special cases for each topology are also provided. The advantage of these designs comes from the added extra degree of freedom presented by the fractional-order α. Matsuda's approximation of sα is used to implement fractional-order capacitors. Also, experimental work is included to verify the theoretical results. © 2018 IEEE.

In this work, a novel implementation of a tunable fractional-order bandpass filter of order 2α is proposed. The transfer function of the presented filter is approximated using the second-order Continued Fraction Expansion (CFE) approximation technique. The filter transfer function is realized using the Inverse Follow the Leader Feedback (IFLF) structure. The Operational Transconductance Amplifiers (OTAs) are used to implement the filter circuit. Furthermore, the proposed filter is tunable by varying the value of only one bias current, which adjust the value of α. The simulations are performed

Recently, memristive oscillators are a significant topic in the nonlinear circuit theory where there is a possibility to build relaxation oscillators without existence of reactive elements. In this paper, a family of voltage-controlled memristor-based relaxation oscillator including two memristors is presented. The operation of two memristors-based voltage relaxation oscillator circuits is demonstrated theoretically with the mathematical analysis and with numerical simulations. The generalized expressions for the oscillation frequency and conditions are derived for different cases, where a

This paper demonstrates a low power 6-bit single-ended voltage-based Capacitance-to-Digital Converter (CDC) circuit based on a charge redistribution technique and Successive Approximation Register (SAR) logic operating at 370 kHz sampling rate. A proposed realization of a SAR logic control unit integrated with a low power comparator is introduced where the system blocks are entirely built on the transistor level. The system, which is fully automated with a universal clock signal, is tested for real time Cadence simulations using a 130nm model from which static and dynamic parameters are

A low-pass fractional-order filter topology based on a single metal oxide semiconductor transistor is presented in this Letter. The filter is realized using a fractional-order capacitor fabricated using multi-walled carbon nanotubes. The electronic tuning capability of the filter’s frequency characteristics is achieved through a biasing current source. Experimental results are presented and compared with the theory. © 2019, Springer Science+Business Media, LLC, part of Springer Nature.

Chebyshev filter is one of the most commonly used prototype filters that approximate the ideal magnitude response. In this paper, a simple and fast approach to create fractional order Chebyshev-like filter using its integer order poles is discussed. The transfer functions for the fractional filters are developed using the integer order poles from the traditional filter. This approach makes this work the first to generate fractional order transfer functions knowing their poles. The magnitude, phase, step responses, and group delay are simulated for different fractional orders showing their

In this letter, all possible single transistor RC-only second-order allpass filters obtainable from a four impedance common-source topology are reported. It is shown that there are only seven such filters with only one of them being a minimum component canonical 2R-2C filter. Two of the found filters are designed and simulated in a 65-nm CMOS process. © 2019 John Wiley & Sons, Ltd.