Verification architects need to make use of randomness supported by System Verilog and be able to define a generic path for the test to follow. This path represents a subset of features, and allows the test to randomly explore the design space to explore corners in depth. Setting up a test case for such designs requires a well-defined stimulus generation methodology. Off-the-shelf scenario

In the frame of the development of thin crystalline silicon solar cell technologies, surface nanopatterning of silicon is gaining importance. Its impact on the material quality is, however, not yet fully controlled.We investigate here the influence of surface nanotexturing on the series resistance of a contacting scheme relevant for thin-film crystalline silicon heterojunction solar cells

The discrete logistic map is one of the most famous discrete chaotic maps which has widely spread applications. This paper investigates a set of four generalized logistic maps where the conventional map is a special case. The proposed maps have extra degrees of freedom which provide different chaotic characteristics and increase the design flexibility required for many applications such as

Cu2ZnSnSe4 thin film solar cells are usually fabricated on a soda lime glass substrate with a molybdenum (Mo) back contact. It is suspected that degradation in electrical performance occurs due to the formation of a barrier between the absorber and Mo back contact. To overcome such degradation, Titanium Nitride (TiN), Titanium Tungsten (TiW), Chromium (Cr), Titanium (Ti) and Aluminum (Al)

Cu2ZnSi(S,Se)4 and Cu2Si(S,Se)3 are potential materials to obtain cost effective high band gap absorbers for tandem thin film solar cell devices. A method to synthesize Cu2SiS3, Cu2SiSe3and Cu2ZnSiSe4thin film absorbers is proposed. This method is based on a multistep process, using sequential deposition and annealing processes. X-ray diffraction analysis performed on the final thin films have

In this paper, we investigate the performance of an ALOHA random access wireless network consisting of nodes with and without RF energy harvesting capability. We develop and analyze a Markov model for the system when nodes with RF energy harvesting capability are infinitely backlogged. Our results indicate that the network throughput is improved when the conventional nodes are underloaded. On the

We have investigated different nonidealities in Cu2ZnSnSe4-CdS-ZnO solar cells with 9.7% conversion efficiency, in order to determine what is limiting the efficiency of these devices. Several nonidealities could be observed. A barrier of about 300 meV is present for electron flow at the absorber-buffer heterojunction leading to a strong crossover behavior between dark and illuminated current

This paper introduces a memristor based redundant binary adder for canonic signed digit code, that coding eliminates the carry and provides a carry-free addition. The proposed binary adder circuit tries to achieve high addition speed that is independent on the length of the data using the accumulation property of a Nano-element called a memristor. The general block diagram of the proposed circuit

This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU. New possible solutions for multi-level logic designs can be established by utilizing the memristor dynamics as a basis in the circuit realization. The proposed memristor-based redundant binary adder circuit tries to achieve the

Multi-phase oscillator is an essential block in digital communication systems especially phase shift keying PSK based systems. In this paper, a procedure for designing a multi-phase oscillator with any required phase shift is proposed, unlike the previous oscillator which generates equal phase shifts. This oscillator circuit is built using fractional-order elements to generate any distribution of