A proposed methodology to improve UVM-based test generation and coverage closure
Verification architects need to make use of randomness supported by System Verilog and be able to define a generic path for the test to follow. This path represents a subset of features, and allows the test to randomly explore the design space to explore corners in depth. Setting up a test case for such designs requires a well-defined stimulus generation methodology. Off-the-shelf scenario libraries and a synchronization and scheduling process methodology for the parallel stimuli need to be reused across several test cases. In this paper, we define a methodology for creating test scenarios and making use of object oriented principles to build composite layered scenario sequences with a generic parallel stimuli synchronization process. We built our methodology as a generic library code to be reused in many designs. A recent memory controller design is used to demonstrate our methodology. The results of applying this methodology on test cases show enhancements on coverage closure and performance. © 2015 IEEE.