Prof. Ahmed Radwan

This paper discusses the continuous effect of fractional order parameter on two chaotic systems. Switched synchronization of three different fractional order chaotic systems is presented as an extension for synchronizing two different systems using active control. The proposed technique, which is based on the switching parameters and the scaling factors that control the choices of master and slave

The discrete logistic map is one of the most famous discrete chaotic maps which has widely spread applications. This paper investigates a set of four generalized logistic maps where the conventional map is a special case. The proposed maps have extra degrees of freedom which provide different chaotic characteristics and increase the design flexibility required for many applications such as

This paper introduces a memristor based redundant binary adder for canonic signed digit code, that coding eliminates the carry and provides a carry-free addition. The proposed binary adder circuit tries to achieve high addition speed that is independent on the length of the data using the accumulation property of a Nano-element called a memristor. The general block diagram of the proposed circuit

This paper introduces a memristor based N-bits redundant binary adder architecture for canonic signed digit code CSDC as a step towards memristor based multilevel ALU. New possible solutions for multi-level logic designs can be established by utilizing the memristor dynamics as a basis in the circuit realization. The proposed memristor-based redundant binary adder circuit tries to achieve the

Multi-phase oscillator is an essential block in digital communication systems especially phase shift keying PSK based systems. In this paper, a procedure for designing a multi-phase oscillator with any required phase shift is proposed, unlike the previous oscillator which generates equal phase shifts. This oscillator circuit is built using fractional-order elements to generate any distribution of

Recently, many reactance-less memristive relaxation oscillators were introduced, where the charging and discharging processes depend on memristors. In this paper, we investigate the power dissipation in different memristor based relaxation oscillators. General expressions for these memristive circuits as well as the power dissipation formulas for three different topologies are derived analytically

This chapter is divided into three sections focusing on some memcapacitor-based applications. The first one discusses the mathematical analyses and design of resistive-less memcapacitor-based relaxation oscillators where different cases have been investigated and validated. Analytical expressions for the oscillation frequency, duty cycle, stored energy, and conditions of oscillation have been

This chapter investigates the advantages of memristor-based digital applications using multi-level arithmetic concepts. Recently, there are huge concerns regarding the memristor in digital signal processing (DSP) circuits to enhance the performance and realize very high density, nonvolatile memories in neural networks. This can be achieved by mapping the high/low logic into the memristor high/low

This chapter reviews the memcapacitor, mathematical representations of time-invariant, physical realizations, and mathematical models. Moreover, the nonlinear boundary effect of the memcapacitor under step, sinusoidal, and general periodic excitation responses are discussed with analytical, numerical, and circuit simulations for different examples. The general analyses of series and parallel