Prof. Ahmed H. Madian

This paper proposes a hardware platform implementation on FPGA for two fractional-order derivative operators. The Grünwald-Letnikov and Caputo definitions are realized for different fractional orders. The realization is based on non-uniform segmentation algorithm with a variable lookup table. A generic implementation for Grünwald-Letnikov is proposed and a 32 bit Fixed Point Booth multiplier radix

This paper is an extension of V-shape multi-scroll butterfly attractor in the fractional-order domain. The system complexity is increased by the new dynamics introduced by the fractional operator which make it more suitable for random signal generator. The effect of system parameters on controlling the attractor shape is investigated and compared with the integer order attractor. Maximum Lyapunov

This paper presents a comparative study of four fractional order filters used for edge detection. The noise performance of these filters is analyzed upon the addition of random Gaussian noise, as well as the addition of salt and pepper noise. The peak signal to noise ratio (PSNR) of the detected images is numerically compared. The mean square error (MSE) of the detected images as well as the

This paper presents a comparative study of edge detection algorithms based on integer and fractional order differentiation. A performance comparison of the two algorithms has been proposed. Then, a soft computing technique has been applied to both algorithms for better edge detection. From the simulations, it shows that better performance is obtained compared to the classical approach. The noise

Arithmetic Logic Unit (ALU) is the most important component of processors. All arithmetic and logical computations are performed inside the ALU. This paper presents the design and the implementation of the ALU. The design is based on Approximated Precision Shader and Look-Up Table (LUT) multiplier. The lookup table, Wallace tree, and Carry Look-ahead Adder (CLA) are used in combination to speed up

In this paper, the effect of the fruits aging on bio-impedance is experimentally studied. Bio-impedance analysis, as accurate and fast method is used to investigate and monitor group of apples properties during aging. This method provides an alternative method for investigating apples physical properties that are highly related to chemical properties. AD5933 impedance analyzer chip within the

This paper presents a study for general fractional order oscillator based on two port network where two topologies of oscillator structure with two impedances are discussed. The two impedances are chosen to be fractional elements which give four combinations for each topology. The general oscillation frequency, condition and the phase difference between the two oscillatory outputs are deduced in

This paper demonstrates a low power 6-bit single-ended voltage-based Capacitance-to-Digital Converter (CDC) circuit based on a charge redistribution technique and Successive Approximation Register (SAR) logic operating at 370 kHz sampling rate. A proposed realization of a SAR logic control unit integrated with a low power comparator is introduced where the system blocks are entirely built on the

This paper presents a generalization of well-known phase shift oscillator based on single CCII into the fractional order domain. The general state matrix, characteristic equation and design equations are presented. The general oscillation frequency, condition and the phase difference between the oscillatory outputs are introduced in terms of the fractional order parameters. These parameters add