Synthesizable SVA protocol checker generation methodology based on TDML and VCD file formats
System Verilog Assertions (SVA) is widely used by hardware designers and verification engineers to apply Assertion Based Verification (ABV) methodology on their hardware designs. However, the complexity in understanding different protocol standards in general and JEDEC memory protocol standards in specific imposes numerous difficulties on designers and verification engineers when translating design specifications into SVA. This motivated us to devise new techniques that can be used to automatically generate SVA for DDR memory protocols with no ambiguity when capturing design requirements from JEDEC standards. Moreover, the proposed assertions generation methods generate "synthesizable SVA", hence allowing hardware designers and verification engineers to use the generated assertions to check the functionality of their design implementation on hardware emulation platforms. The viability and the potential of our work are demonstrated with an Industrial case study using JEDEC LPDDR3 Memory Protocol Standard. © 2016 IEEE.