Log-domain implementation of fractional-order element emulators
Novel fractional-order capacitor and inductor em-ulators are presented in this work, which offer fully electronic tunability of their characteristics and, simultaneously, reduced circuit complexity compared to those already introduced in the literature. This has been achieved through the utilization of the log-domain filtering for implementing the approximation of the required fractional-order differentiation/integration stages. The behavior of the presented topology is evaluated using the Cadence software and MOS transistor models provided by the 0.35μm Austria Mikro Systeme CMOS process. © 2019 IEEE.