FPGA implementation of a chaotic oscillator with odd/even symmetry and its application
We propose a mathematical system capable of exhibiting chaos with a chaotic attractor which is odd symmetrical in the x − y phase plane but even symmetrical in the x − z and y − z phase planes respectively. A hardware implementation of the system is done on a digital FPGA platform for verification. The system is also attractive in the sense that (i) its dynamics are single-parameter controlled and (ii) it inherently generates two chaotic clock signals. As an application, an FPGA design methodology using this oscillator for speech encryption is demonstrated. The security of the proposed encryption scheme is evaluated and results confirm its robustness. Due to the efficient hardware resource utilization, the encrypted system delivers a throughput of 1.3Gbit/sec using a Xilinx Kintex 7. © 2020 Elsevier B.V.