FPGA-Based Memristor Emulator Circuit for Binary Convolutional Neural Networks

Tolba M.F.
Halawani Y.
Saleh H.
Mohammad B.
Al-Qutayri M.

Binary convolutional neural networks (BCNN) have been proposed in the literature for resource-constrained IoTs nodes and mobile computing devices. Such computing platforms have strict constraints on the power budget, system performance, processing and memory capabilities. Nonetheless, the platforms are still required to efficiently perform classification and matching tasks needed in various applications. The memristor device has shown promising results when utilized for in-memory computing architectures, due to its ability to perform storage and computation using the same physical element. This is in addition to their nonlinear dynamic characteristics that can be used for various applications. Emulating the memristor operation through FPGAs implementation provides flexibility for rapid prototyping and exploration of the design space. In this paper, a FPGA-based memristor emulator circuit is implemented using a multi-bit XNOR gate as the main block for binary convolution which is followed by a memristor-based pooling layer. The BCNN layer is realized by bitwise XNOR-cell followed by wide NOR gate. The implementation has been successfully synthesized and verified using Xilinx Nexys4 FPGA with less than 1% utilization and 144.9 MHz frequency of operation. In order to test the functionality of the proposed cores, a digital implementation for the circuit was realized and verified experimentally. The experimental results show similar performance when compared to software simulation. © 2013 IEEE.