Resonant square-wave clock generator for low power applications

Power reduction is the main challenge facing circuit designers in their quest to utilize the full performance of new process technologies. A major portion of the power consumed in today's systems is due to the clock generation and distribution. Resonant clocking has been a promising technique to reduce the clock power dramatically. In this paper, a novel resonant clock generator circuit is proposed to reduce the dynamic power used for clock generation by almost 75%. Two configurations of the circuit are presented. The merit of this generator is most obvious in the ease of its implementation and insertion into nowadays systems and the huge power savings it achieves with minimal area overhead. © 2011 IEEE.