This paper introduces data converter circuit based on memristors. A proposed Digital to Analog Converter (DAC) circuit based on non-overlapped input signals, which is suitable for common source connected transistors. Analytical formulas are introduced to relate the digital input with the analog output including the transistors dimension. In addition, PSpice simulations are performed to validate

The electric characteristics of electric-double layer capacitors (EDLCs) are determined by their capacitance which is usually measured in the time domain from constant-current charging/discharging and cyclic voltammetry tests, and from the frequency domain using nonlinear least-squares fitting of spectral impedance. The time-voltage and current-voltage profiles from the first two techniques are

Arithmetic Logic Unit (ALU) is the most important component of processors. All arithmetic and logical computations are performed inside the ALU. This paper presents the design and the implementation of the ALU. The design is based on Approximated Precision Shader and Look-Up Table (LUT) multiplier. The lookup table, Wallace tree, and Carry Look-ahead Adder (CLA) are used in combination to speed up

Power supply noise has become a major challenge for proper operation of circuits with continuous scaling of CMOS technology along with supply voltage scaling. Conventional passive decoupling capacitors exhibit significant die area penalty resulting in a limited regulation effect. This paper presents a fully integrated charge-sharing-based active decap scheme for power supply noise suppression. The

A hybrid Time to Digital Converter (TDC) - Bang Bang (BB) All Digital Phase Locked Loop (ADPLL) architecture is proposed to optimize power, area, lock time, and design complexity. The Hybrid ADPLL architecture utilizes a low resolution two synthesizable Time to Digital Converters to achieve fast lock time, and then switches to a Bang-Bang like architecture once it is in the locked state. Such

A novel topology suitable for emulating fractional-order capacitors and inductors using current excitation is achieved using a fractional-order differentiator/integrator block and appropriately configured Operational Transconductance Amplifiers. The scheme is capable of emulating both fractional-order capacitors and fractional-order inductors without any modifications to its structure. This

Characterizing and modeling electrical energy storage devices is essential for their proper integration in larger systems. However, basic circuit elements, i.e. resistors, inductors, and capacitors, are not well-suited to explain their complex frequency-dependent behaviors. Instead, fractional-order models, which are based on non-integer-order differential equations in the time-domain and include

Chaos is described as a unstable dynamic behavior with dependence on initial conditions. The control and synchronization of chaotic systems requires the knowledge of parameters in advance. Recently researcher's has been shifted from integer order chaotic system to fraction order chaotic system. In this work, based on the stability theory of integer-order linear systems and Lyapunov stability

A low frequency relaxation oscillator is designed using a super-capacitor. An accurate analytical expression for the oscillation frequency is derived based on a fractional-order super-capacitor model composed of a resistance in series with a Constant Phase Element (CPE) whose pseudo-capacitance and dispersion coefficient are determined using impedance spectroscopy measurements. Experimental

The porous nature of the electrode material in supercapacitors and the apparent conductivity of the electrolyte cause their impedance to show a complex frequency-dependent behavior, which in turn makes it incorrect to treat them as ideal capacitors, even at a frequency of a few millihertz. This is particularly crucial if the intended application requires a configuration that uses stacked