FPGA realization of speech encryption based on modified chaotic logistic map

This paper presents an FPGA design and implementation of a chaotic speech encryption and decryption system based on bit permutations. Different encryption schemes are realized and compared. In addition, various testing methods including entropy, mean squared error, and correlation coefficients are used to analyze the efficiency of the system. The techniques for area and delay minimization are used. Carry look-ahead adder, multi-operand adder and booth multiplier are used to improve the performance of the encryption schemes design. A comparison between the different encryption architectures and the state of the art is introduced. The results demonstrate the good security of the proposed systems, which enables their utilization in speech telecommunication. The designs have been simulated using Xilinx ISE 14.7 and realized on FPGA Xilinx virtex-5 xc5lx50T. A throughput of 7.9 Gbit/sec for bit permutation design, 2.6 Gbit/sec for bit permutation and chaotic modified logistic map is achieved compared with 1.1 Gbit/sec and 1.49 Gbit/sec for previous work. © 2018 IEEE.